Data processing systems which use a common bus for communication of address and data information from system components to a main memory and among the system component themselves require appropriate bus protocols, i.e., bus operating signals, for providing appropriate use of the bus by the system components involved. One such system, for example, is shown in U.S. Pat. No. 4,371,925, issued on Feb. 1, 1983 to Carberry et al., in which a system utilizing a single system bus has a plurality of system components thereon both for controlling the operation of the data processing system and for providing communication with input/output (I/O) devices via one or more suitable I/O interface units. In order to make effective use of the common bus, the system utilized a 2-phase timing signal which permitted address information to be placed on the bus only during the first phase and data information to be placed on the bus normally during the second phase, although sometimes during both phases. To avoid "bus fighting" conditions between two components requesting access thereto, the system utilized two control signals, an address enable signal and a data enable signal, a component having control of the bus asserting the first signal when a valid address was being placed thereon and asserting the second signal when valid data was being placed thereon. Assertion of such signals inhibited the placing of addresses and data on the bus by any other system component. The use of a dual phase operating timing signal and the need for such control signals tend to provide added control complications which it is desirable to simplify. Moreover, the system bus protocols used therein are not readily and efficiently adaptable for a system which utilizes two buses available for common use, for example, in order to supply a dual port main memory. It is desirable, therefore, to devise a system having a more effective bus protocol and operation for both single and dual common bus operations.